At Kepler, you’ll have the opportunity to work with a small dedicated team of engineers building the Kepler spacecraft. You will be responsible for the design and implementation of FPGA cod with a focus on DPS algorithms to modulate and demodulate signals on board our software defined radio (SDR). You will interface with backend electrical engineers on your team to identify timing and layout constraints. To be effective you will need to participate in all phases of FPGA design flow (Synthesis, Place & Route, and Timing Closure). A good understanding of the entire communications chain from coding to decoding and everything in between will make a candidate stand out.
- Bachelor’s Degree in Electrical Engineering, Math, or equivalent
- 2+ yr. experience with Verilog, SystemVerilog or VHDL
- 2+ yr. experience with communications systems that are multiple access (e.g. CDMA, TDMA, FDMA)
- 1+ yr. experience with channel coding (LDPC, Turbo Codes, Reed-Solomon)
- Masters of Science in electrical engineering with emphasis in communication systems and digital signal processing.
- Experience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAM, PCM/FM, APSK, SC-FDMA, OFDM and OFDMA.
- &Experience in implementing satellite broadcast standards (e.g. DVB-S2)
- Exposure to state-of-the-art DSP algorithms in carrier recovery, frame and symbol synchronization
- Experience modeling RF and channel impairments such as multipath, phase noise, group delay, fading and nonlinear distortion.
- Experience in Digital Pre-Distortion.
- Understanding of link budgets and RF system noise analysis
- Experience with FPGA tools (e.g Quartus II), HDL Simulation Tools (ModelSim)
- Exposure to timing closure techniques.
- Excellent scripting skills (Tcl, csh/bash, Perl, Python etc.)
- Relevant experience with hobbies or University design team (e.g. FSAE, SAE, CSDC etc.)